A Model-Theoretic Semantics for Modal LogicPAULOS J.Notre Dame Journal of Formal Logic. 1976, Vol 17, Num 3, pp 465-468Article

A Model-Theoretic Semantics for Modal LogicPAULOS J.Notre Dame Journal of Formal Logic. 1976, Vol 17, Num 3, pp 465-468Article

A MODEL-THEORETIC ACCOUNT OF CONFIRMATIONPAULOS J.1979; NOTRE DAME J. FORM. LOGIC; USA; DA. 1979; VOL. 20; NO 2; PP. 451-457; BIBL. 2 REF.Article

A MODEL-THEORETIC SEMANTIES FOR MODAL LOGIC.PAULOS J.1976; NOTRE DAME J. FORM. LOGIC.; U.S.A.; DA. 1976; VOL. 17; NO 3; PP. 465-468; BIBL. 5 REF.Article

A Model-Theoretic Account of ConfirmationPAULOS, J.Notre Dame Journal of Formal Logic Notre-Dame, Ind. 1979, Vol 20, Num 2, pp 451-457Article

A framework for extendable freeform surface feature modellingNYIRENDA, Paulos J; BRONSVOORT, Willem F.Computers in industry. 2009, Vol 60, Num 1, pp 35-47, issn 0166-3615, 13 p.Article

A Model-Theoretic Explication of the Theses of Kuhn and WhorfPAULOS, J. A.Notre Dame Journal of Formal Logic Notre-Dame, Ind. 1980, Vol 21, Num 1, pp 155-165Article

Low-voltage coefficient capacitors for VLSI processesSLATER, D. B; PAULOS, J. J.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 165-173, issn 0018-9200, 9 p.Article

A monolithic patch-clamping amplifier with capacitive feedbackPRAKASH, J; PAULOS, J. J; JENSEN, D. N et al.Journal of neuroscience methods. 1989, Vol 27, Num 2, pp 165-172, issn 0165-0270, 8 p.Article

Unified nonquasi-static modeling of the long-channel four-terminal MOSFET for large- and small-signal analyses in all operating regimesKAM-WING CHAI; PAULOS, J. J.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 11, pp 2513-2520, issn 0018-9383, 8 p., 1Article

Comparison of quasi-static and non-quasi-static capacitance models for the four-terminal MOSFETKAM-WING CHAI; PAULOS, J. J.IEEE electron device letters. 1987, Vol 8, Num 9, pp 377-379, issn 0741-3106Article

Improved floating-gate devices using standard CMOS technologyMONTALVO, A. J; PAULOS, J. J.IEEE electron device letters. 1993, Vol 14, Num 8, pp 372-374, issn 0741-3106Article

Artifical neural networks using MOS analog multipliersHOLLIS, P. W; PAULOS, J. J.IEEE journal of solid-state circuits. 1990, Vol 25, Num 3, pp 849-855, issn 0018-9200, 7 p.Article

Measurement of minimum-geometry MOS transistor capacitancePAULOS, J. J; ANTONIADIS, D. A.I.E.E.E. transactions on electron devices. 1985, Vol 32, Num 2, pp 357-363, issn 0018-9383Article

Toward a general-purpose analog VLSI neural network with on-chip learningMONTALVO, A. J; GYURCSIK, R. S; PAULOS, J. J et al.IEEE transactions on neural networks. 1997, Vol 8, Num 2, pp 413-423, issn 1045-9227Article

Template-based MOSFET device modelGRAHAM, M. G; PAULOS, J. J; NYCHKA, D. W et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1995, Vol 14, Num 8, pp 924-933, issn 0278-0070Article

Hierarchical yield estimation of large analog integrated circuitsKURKER, C. M; PAULOS, J. J; GYURCSIK, R. S et al.IEEE journal of solid-state circuits. 1993, Vol 28, Num 3, pp 203-209, issn 0018-9200Conference Paper

A self-tuning digital telemetry IC for use in a microprocessor-based implantable instrument : Analog and signal processing circuitsFERNALD, K. W; PAULOS, J. J; STACKHOUSE, B. A et al.IEEE journal of solid-state circuits. 1992, Vol 27, Num 12, pp 1826-1832, issn 0018-9200Article

New strategies for improving speech enhancementWHITE, M. W; HOLDAWAY, R. M; YIN GUO et al.International journal of bio-medical computing. 1990, Vol 25, Num 2-3, pp 101-124, issn 0020-7101Article

Table-based simulation of delta-sigma modulatorsBISHOP, R. J; PAULOS, J. J; STEER, M. B et al.IEEE transactions on circuits and systems. 1990, Vol 37, Num 3, pp 447-451, issn 0098-4094, 5 p.Article

Switch-level simulation of total dose effects on CMOS VLSI circuitsBHUVA, B. L; PAULOS, J. J; GYURCSIK, R. S et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 9, pp 933-938, issn 0278-0070Article

Table-based modeling of delta-sigma modulators using ZSIMBRAUNS, G. T; BISHOP, R. J; STEER, M. B et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1990, Vol 9, Num 2, pp 142-150, issn 0278-0070, 9 p.Article